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LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
DESCRIPTION
The LF9502 is a high-speed, 10-bit programmable line buffer. Some applications the LF9502 is useful for include sample rate conversion, data time compression/expansion, software controlled data alignment, and programmable serial data shifting. By using the MODSEL pin, two different modes of operation can be selected: delay mode and data recirculation mode. The delay mode provides a minimum of 2 to a maximum of 2049 clock cycles of delay between the input and output of the device. The data recirculation mode provides a feedback path from the data output to the data input for use as a programmable circular buffer. By using the length control input (LC10-0) and the length control enable (LCEN) the length of the delay buffer or amount of recirculation delay can be programmed. Providing a delay value on the LC10-0 inputs and driving LCEN LOW will load the delay value into the length control register on the next selected clock edge. Two registers, one preceeding the programmable delay RAM and one following, are included in the delay path. Therefore, the programmed delay value should equal the desired delay minus 2. This consequently means that the value loaded into the length control register must range from 0 to 2047 (to provide an overall range of 2 to 2049). The active edge of the clock input, either positive or negative edge, can be selected with the clock select (CLKSEL) input. All timing is based on the active clock edge selected by CLKSEL. Data can be held temporarily by using the clock enable (CLKEN) input.
FEATURES
u 50 MHz Maximum Operating Frequency u Programmable Buffer Length from 2 to 2049 Clock Cycles u 10-bit Data Inputs and Outputs u Data Delay and Data Recirculation Modes u Supports Positive or Negative Edge System Clocks u Expandable Data Word Width or Buffer Length u 44-pin PLCC, J-Lead
LF9502 BLOCK DIAGRAM
MODSEL LCO10-0
11
LCEN
REGISTER
REGISTER
11
PROGRAMMABLE 2K DELAY RAM
REGISTER
DI9-0
10
10
10
REGISTER
10
OE
10 10
MUX
DO9-0
10
CLKSEL CLKEN CLK
CLOCK GENERATOR
TO ALL REGISTERS
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LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
Outputs DO9-0 -- Data Output The 10-bit data output appears on DO9-0 on the Nth clock cycle, where N is the overall delay (desired delay). Controls LCEN -- Length Control Enable When LCEN is driven LOW, the next active clock edge will cause the loading of the delay value present at the LC10-0 input. OE -- Output Enable The Output Enable controls the state of DO9-0. Driving OE LOW enables the output port. When OE is HIGH, DO9-0 is placed in a high-impedance state. The internal transfer of data is not affected by this control. MODSEL -- Mode Select The Mode Select pin is used to choose the desired mode of operation: data delay mode or data recirculation mode. Driving MODSEL LOW places the device in the delay mode. The device operates as a programmable pipeline register. New data from the DI9-0 input is loaded on every active edge of CLK. Driving MODSEL HIGH places the device in the data recirculation mode. The device operates as a programmable circular buffer. The output of the device is routed back to the input. MODSEL may be changed during device operation (synchronously), however, the required setup and hold times, with respect to CLK, must be met. CLKSEL -- Clock Select The CLKSEL control allows the selection of the active edge of CLK. A LOW on CLKSEL selects negativeedge triggering of the device. Driving CLKSEL HIGH selects positive-edge triggering. All timing specifications are referrenced to the selected active edge of CLK. CLKEN -- Clock Enable The Clock Enable control enables and disables the CLK input. Driving CLKEN LOW enables CLK and causes the device to operate in a normal fashion. When CLKEN is HIGH, CLK is disabled and the device will hold all internal operations and data. CLKEN may be changed during device operation (synchronously), however, the required setup and hold times, with respect to CLK, must be met. The changing of CLKEN takes effect on the active edge of CLK following the edge in which it was latched.
SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock CLK -- Master Clock The active edge of CLK, selected by CLKSEL, strobes all registers. All timing specifications are referenced to the active edge of CLK. Inputs DI9-0 -- Data Input 10-bit data, from the data input, is latched into the device on the active edge of CLK when MODSEL is LOW. LC10-0 -- Length Control Input The 11-bit value is used to specify the length of the delay buffer, between DI9-0 and DO9-0, or the amount of recirculation delay. An integer value ranging from 0 to 2047 is used to select a delay ranging from 2 to 2049 clock cycles. The value placed on the LC10-0 inputs is equal to the desired delay minus 2. The data presented on LC10-0 is loaded into the device on the active edge of CLK, selected by CLKSEL, in conjunction with LCEN being driven LOW.
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LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... -65C to +150C Operating ambient temperature ........................................................................................... -55C to +125C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +7.0 V Input signal with respect to ground ............................................................................... -0.5 V to VCC + 0.5 V Signal applied to high impedance output ...................................................................... -0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode Active Operation, Commercial Temperature Range (Ambient) 0C to +70C Supply Voltage 4.75 V VCC 5.25 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance
(Note 3)
Test Condition VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA
Min 2.4
Typ
Max
Unit V
0.4 2.0 0.0 VCC 0.8 10 10 125 500 10 10
V V V A A mA A pF pF
Ground VIN VCC (Note 12) Ground VOUT VCC (Note 12)
(Notes 5, 6) (Note 7)
TA = 25C, f = 1 MHz TA = 25C, f = 1 MHz
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432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE
Symbol
DEVICES INCORPORATED
COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
2K Programmable Line Buffer
LF9502- 25
0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321
15 0 5 0 4 0 5 6 5 5 5 0 0 15* 10 12 12
09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321
12 40 15 13 12 12 13 2 2 4 2 2 2 40* 22 25 25 10 31 12 10 10 10 10 2 2 4 2 2 2 31* 16 24 24
*When CLKSEL is HIGH, assume CLK is inverted.
FUNCTIONAL TIMING -- CLKSEL LOW
tDIS
tENA
tOH
tOUT
tMH
tMS
tLEH
tLES
tLH
tLS
tEH
tES
tDH
tDS
tPW
tCYC
MODSEL
Parameter
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
Output Hold Time (Note 8)
Clock to Data Out
Mode Select Hold Time
Mode Select Setup Time
Length Control Enable to Clock Hold Time
Length Control Enable to Clock Setup Time
Length Control Input Hold Time
Length Control Input Setup Time
Clock Enable to Clock Hold Time
Clock Enable to Clock Setup Time
Data Input Hold Time
Data Input Setup Time
Clock Pulse Width
Cycle Time
DO9-0
CLK*
DI9-0
OE
tMS
tPW
tDS
tOH
tCYC
tOUT
tPW
tDH
tDIS
4
HIGH IMPEDANCE
Min Max Min Max Min Max Min Max Min Max
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tENA tMH
25
10
2
8
2
4
2
8
8
8
8
2
2
15
15
15
20
2
6
2
4
2
8
6
6
6
6
2
2
20
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14 14
LF9502
432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE
Symbol
DEVICES INCORPORATED
COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
2K Programmable Line Buffer
LF9502- 25
0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321
15 0 5 0 4 0 5 6 5 5 5 0 0 15* 10 12 12
09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321
12 40 15 13 12 13 13 2 2 4 2 2 2 40* 22 25 25 10 31 12 10 10 10 10 2 2 4 2 2 2 31* 16 24 20
*When CLKSEL is HIGH, assume CLK is inverted.
LENGTH CONTROL TIMING -- CLKSEL LOW
CLOCK ENABLE TIMING -- CLKSEL LOW
tDIS
tENA
tOH
tOUT
tMH
tMS
tLEH
tLES
tLH
tLS
tEH
tES
tDH
tDS
tPW
tCYC
INTERNAL CLOCK
Parameter
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
Output Hold Time (Note 8)
Clock to Data Out
Mode Select Hold Time
Mode Select Setup Time
Length Control Enable to Clock Hold Time
Length Control Enable to Clock Setup Time
Length Control Input Hold Time
Length Control Input Setup Time
Clock Enable to Clock Hold Time
Clock Enable to Clock Setup Time
Data Input Hold Time
Data Input Setup Time
Clock Pulse Width
Cycle Time
LC10-0
LCEN
CLK*
CLKEN
CLK*
tLES
tLS
tES
tLEH
tLH
tPW
5
tES
Min Max Min Max Min Max Min Max Min Max
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tMH
tMH
25
10
2
8
2
4
2
8
8
8
8
2
2
15
15
15
20
2
6
2
4
2
8
6
6
6
6
2
2
20
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14 14
LF9502
LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
NOTES
9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and IOL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at -0.6 V and a. A 0.1 F ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of -0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 25 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the 200mV level from the measured steady-state output voltage with 10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
DUT
S1 IOL CL IOH VTH
FIGURE B. THRESHOLD LEVELS
tENA OE
Z 0
1.5 V 1.5 V 1.5 V
tDIS
3.5V Vth VOL*
0.2 V
0 1
Z Z
1.5 V
VOH*
0.2 V
Z
1
0V Vth VOL* Measured VOL with IOH = -10mA and IOL = 10mA VOH* Measured VOH with IOH = -10mA and IOL = 10mA
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LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
ORDERING INFORMATION
44-pin
LCEN CLKSEL NC NC CLKEN CLK LC2 LC3 LC4 LC5 MODSEL DO0 DO1 DO2 DO3 DO4 VCC GND DO5 DO6 DO7 DO8
7 8 9 10 11 12 13 14 15 16 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36
Top View
35 34 33 32 31 30
17 29 18 19 20 21 22 23 24 25 26 27 28
DI0 DI1 DI2 DI3 DI4 VCC GND DI5 DI6 DI7 DI8
Speed
Plastic J-Lead Chip Carrier (J1)
0C to +70C -- COMMERCIAL SCREENING
25 ns 20 ns LF9502JC25 LF9502JC20
-40C to +85C -- COMMERCIAL SCREENING
DO9 OE LC0 LC1 LC10 LC9 LC8 LC7 LC6 DI9 NC
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